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Lista aggiornata al 10-10-2002



Pubblicazioni a Congressi

  1. G.C. Cardarilli, M. Re, M. Salerno, Multiplierless Digital Architecture for Membership Function Evaluation, Proceedings of International Conference on Neural Information Processing, Vol.2, pp. 1307-1310, Seoul (Korea), October 17-20 1994.

  2. G.C. Cardarilli, M. Re, R. Lojacono, M. Salerno, A. Salsano, The Aid of Simulation in the Development of Finite Arithmetic Architectures, 9th European Simulation Multiconference ESM '95, Vol. 1, pp. 24-28, Prague (Czech Republic), June 5-7 1995.

  3. G.C.Cardarilli, M. Re, R. Lojacono, M. Salerno, RNS Fast Divider, European Conference on Circuit Theory and Design ECCTD '95, Vol.2, pp.675-678, Istanbul (Turkey), 27-31 August 1995.

  4. G.C. Cardarilli, M. Re, R. Lojacono, M. Salerno, A VLSI Defuzzification Architecture for Real Time Fuzzy Processors, 3rd European Congress on Intelligent Techniques and Soft Computing EUFIT '95, Vol. 3, pp. 1810-1814, Aachen (Germany), 20-31 August 1995.

  5. G.C. Cardarilli, M. Re, M. Persichini, A. Salsano, M. Salmeri, O.Simonelli, Riconoscimento di Caratteri Manoscritti: Implementazione Hardware di un algoritmo Fuzzy per il Preprocessamento, Elettronica '95 XXVII Riunione Annuale del Gruppo Elettronica, Riva del Garda (Italy), 18-22 Giugno 1995.

  6. M.Re, R. Lojacono, G.C. Cardarilli, Application of Fuzzy Logic to Real-Time Radar Target Tracking, Proceedings of TOOLMET'96 Symposium Tool Environments and Development Methods for Intelligent Systems, Vol.1, pp. 165-170, Oulu (Finland), April 1-2 1996.

  7. M. Re, Metodologie di Conversione Ingresso-Uscita in Processsori in Aritmetica Finita, Ph.D. Thesis in Microelectronics and Telecommunications Engineering,University of Rome "Tor Vergata", Rome (Italy), November 1996.

  8. G.C. Cardarilli, M. Re, R. Lojacono, High-Performance Fuzzy Processor with Simplified Architecture, 4rd European Congress on Intelligent Techniques and Soft Computing EUFIT '96, Vol.3 , pp. 2250-2254, Aachen (Germany), September 2-5 1996.

  9. G.C. Cardarilli, M. Re, R. Lojacono, High Speed Fuzzy Filter for Non-Linear Channel Equalization, Proceedings of the Second International ICSC on Fuzzy Logic and Applications ISFL `97, pp. 8-13, Zurich (Switzerland), February 12-14 1997.

  10. G.C. Cardarilli, M. Re, R. Lojacono, Efficient Modulo Extraction for CRT based Residue to Binary Converters, International Symposium on Circuits and Systems ISCAS '97, Vol.3. pp. 2036-2039, Hong Kong (China), June 9-12 1997.

  11. G.C. Cardarilli, M. Re, R. Lojacono, M. Salmeri, A New Architecture for High-Speed COG based Defuzzification, Proceedings of TOOLMET' 97 Symposium Tool Environments and Development Methods for Intelligent Systems, pp. 165-172, Oulu (Finland), April 17-18 1997.

  12. G.C. Cardarilli, M. Re, R. Lojacono, Hardware Implementation of Fuzzy Processors: an Overview, Proceedings of TOOLMET' 97 Symposium Tool Environments and Development Methods for Intelligent Systems, pp. 49-61, Oulu (Finland), April 17-18 1997.

  13. G.C.Cardarilli, M. Re, M. Salmeri, S. Bertazzoni, A. Salsano, D. Piergentili, A Self- Configuring Fuzzy Classifier for Handwritten Character Recognition, Proceedings of TOOLMET' 97 Symposium Tool Environments and Development Methods for Intelligent Systems, pp. 137- 143, Oulu (Finland), April 17-18 1997.

  14. G.C. Cardarilli, M. Re, R. Lojacono, A New RNS FIR Filter Architecture, 13th International Conference on Digital Signal Processing (DSP 97), Vol. 2, pp. 671-674, Santorini, (Greece), July 2-4 1997.

  15. G.C. Cardarilli, M. Re, R. Lojacono, A Residue to Binary Conversion Algorithm for Signed Numbers, European Conference on Circuit Theory and Design ECCTD '97, Vol. 3, pp. 1456-1459, Budapest (Hungary), 31 August - 3 September 1997.

  16. G.C.Cardarilli, M. Re, R. Lojacono, VLSI Architecture for High-Speed Fuzzy Equalization, 5rd European Congress on Intelligent Techniques and Soft Computing EUFIT '97, Vol. 3, pp. 1820-1824, Aachen (Germany), September 8-12 1997.

  17. G. C. Cardarilli, M. Re, G. Ferri, R.Lojacono A High Speed VLSI Architecture for Scaled Residue to Binary Conversion, International Symposium on Circuits and Systems ISCAS '98, , Vol. 2, pp. 414-416 , Monterey (California), May 31-June 3 1998.

  18. G. C. Cardarilli, M. Re, G. Ferri, A 1.6 V 80 mW Rail-To-Rail Constant Gm Bipolar Adaptive Biased OP-AMP Input Stage, International Symposium on Circuits and Systems ISCAS '98, Vol. I, pp. 452-455, Monterey (California), May 31-June 3 1998.

  19. G.C. Cardarilli, M. Re, R. Lojacono, M. D'Elena, G.Scrimaglio, A VLSI Architecture for High Speed Fuzzy Image Processing, 6 th European Congress on Intelligent Techniques and Soft Computing, EUFIT'98, Vol. 2., pp. 1350-1354, Aachen (Germany), September 7-10, 1998.

  20. G.C. Cardarilli, M. Re, R. Lojacono, Evaluation of the Noise Effects in Nonlinear Quantization,International Symposium on Nonlinear Theory and its Applications, NOLTA '98, Vol. 3, pp. 1153-1156, Crans Montana (Switzerland), September 14-17 1998.

  21. G. C. Cardarilli, R. Lojacono, M. Re, M. Salmeri, A. Salsano, R. Scrimaglio, FSDT: A CAD Environment for Fuzzy Systems Development, Proceedings of TOOLMET '99 Symposium Tool Environments and Development Methods for Intelligent Systems, pp. 155-161, Oulu (Finland), 15-16 April 1999.

  22. G. C. Cardarilli, R. Lojacono, M. Re, M. Salmeri , A. Salsano, SAR Images Filtering: a Fuzzy Approach, Proceedings of Toolmet '99 Symposium Tool Environments and Development Methods for Intelligent Systems, pp. 176-181, Oulu (Finland), 15-16 April 1999.

  23. G. C. Cardarilli, M. Re, R. Lojacono, L.Lavagno, A. Sangiovanni Vincentelli, Analysis of the Quantization Noise Effects on the SQNR Behaviour in Analog to Digital Conversion , International Symposium on Circuits and Systems ISCAS'99, Vol. II, pp. 334-338, Orlando (Florida), May 30-June 2 1999.

  24. G. C. Cardarilli, M. Re, R. Lojacono,G.Ferri A New Efficient Architecture for Binary to RNS Conversion, European Conference on Circuit Theory and Design ECCTD'99, Vol. II, pp. 1151-1154, Stresa (Italy), 29 August - 2 September 1999.

  25. G. C. Cardarilli, F. Alfonsetti, M. Re, G.Ferri Bipolar and CMOS Low Voltage-Supply Reduced-Power Voltage Followers, ICECS'99, 6th International Conference on Electronics, Circuits and Systems, pp. 1503-1506, Pafos (Cyprus), September 5-8 1999.

  26. G. C. Cardarilli, M. Re, A. Del Re, G. Rovigatti, V. Piloni, Efficient Implementation of a Filter Bank Architecture for Demultiplexing in Satellites Applications, Thirthy-Third Asilomar Conference on Signals, Systems and Computers Asilomar'99, Vol. 1, pp. 569-573 Pacific Groove (California), October 24-27,1999.

  27. M.Re, G. Cardarilli, M.Salmeri, E.Petrongari, A Novel Bacterial Algorithm to Extract Rule Base from a Training Set, The 9th International Conference on Fuzzy Systems FUZZ IEEE 2000, pp. 759-761, San Antonio (Texas), 7-10 May 2000.

  28. Marco Re, Marcello Salmeri, GianCarlo Cardarilli, A CAD Environment for Fuzzy Systems Hw/Sw Mapping, IEEE, International Symposium on Circuit and Systems ISCAS 2000, Vol. IV, pp.221-224, Geneva (Switzerland), May 28-31 2000.

  29. Marco Re, Gian Carlo Cardarilli, Andrea Del Re, Roberto Lojacono, FPGA Implementation of a Demux Based on a Multirate Filter Bank, IEEE, International Symposium on Circuit and Systems ISCAS 2000, Vol. V, pp. 353-356, Geneva (Switzerland), May 28-31, 2000.

  30. Marco Re, Alberto Nannarelli, Roberto Lojacono, GianCarlo Cardarilli, Residue Arithmetic Techniques for High Performance DSP, CSCC'2000, Volume "Problems in Modern and Applied Mathematics", pp. 314-318, Athens (Greece), July 9-16, 2000.

  31. Roberto Lojacono, Marco Re, GianCarlo Cardarilli, A Self Correcting Analog to RNS Converter, IMEKO 2000, 5th Workshop on ADC Modeling and Testing, pp.287-290, Vol. IX,Hofburg - Wien (Austria), September 26-28, 2000.

  32. R. Lojacono, Marco Re, G. Cardarilli, Modeling and Simulation of the Non Linear Effects in Analog to Digital Converters, IMEKO 2000, 5th Workshop on ADC Modeling and Testing, pp. 261-266, Vol. X, Hofburg (Wien), Austria,September 26-28, 2000.

  33. M.Re, G.C. Cardarilli, A. Nannarelli, Reducing Power Dissipation in FIR Filters Using the Residue Number System, IEEE, Midwest Symposium on Circuits and Systems MWCAS 2000, Lansing (Minnesota), August 8-11, 2000.

  34. Angelo D'Amora, G. C. Cardarilli, M. Re, Alberto Nannarelli,Reducing Power Dissipation in Complex Digital Filters by using the Quadratic Residue Number System Thirty-Fourth Asilomar Conference on Signals Systems and Computers, Vol. 2, pp. 879-883, Pacific Groove (California), October 29-November 1, 2000.

  35. Gian Carlo Cardarilli, Andrea Del Re, E. Petrongari , Marco Re, Numerical Controlled Oscillator based on Fuzzy Approximation, Toolmet2001, Symposium on Tools Environments and Development Methods for intelligent Systems, pp. 91-99, Oulu (Finland), April 2001.

  36. Gian Carlo Cardarilli, Enrico Petrongari, Andrea Del Re, Marco Re, Fuzzy Systems Discovery Using Evolutionary Algorithms, Toolmet2001, Symposium on Tools Environments and Development Methods for intelligent Systems, pp. 111-117, Oulu (Finland), April 19-20, 2001.

  37. A. Nannarelli, M. Re, G. C. Cardarilli, Tradeoffs between Residue Number System and Traditional FIR Filters, IEEE, International Symposium on Circuits and Systems, ISCAS 2001, Vol. II, pp. 305-308, Sydney (Australia), May 6-9, 2001.

  38. M. Re, A. Nannarelli, G. C. Cardarilli, R. Lojacono, FPGA Realization of RNS to Binary Signed Number Conversion Architecture, IEEE,International Symposium on Circuits and Systems,ISCAS 2001, Vol. IV, pp. 350-353, Sydney (Australia), May 6-9, 2001.

  39. M. Ottavi G. C. Cardarilli, P. Marinucci, S. Pontarelli, M. Re, A. Salsano, Development of a Dynamic Routing System for a Fault Tolerant Solid State Mass Memory, IEEE, International Symposium on Circuits and Systems, ISCAS 2001, Vol. IV, pp. 830-833, Sydney (Australia), May 6-9, 2001.

  40. A. Malvoni, G. C. Cardarilli, M. Re, A. Salsano, S. Pontarelli, M. Ottavi, System-on-Chip Oriented Fault Tolerant Sequential Systems Implementation Methodology, DFT 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems,pp. 455-469, 24-26 October, 2001, San Francisco, California.

  41. D. Cellitti, G. C. Cardarilli, M. Re, A. Salsano, S. Pontarelli, M. Ottavi, Design of Totally Self Checking Signature Analysis Checker for Finite State Machines, DFT 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 403-411, 24-26 October, 2001, San Francisco, California.

  42. G. C. Cardarilli, A. Malvoni, M. Ottavi, S. Pontarelli, M. Re, A. Salsano, System-on-Chip Implementation and Fault-Coverage Estimation of a Fault-Tolerant Finite State Machine , 5th World Multi-Conference on Systems, Cybernetics and Informatics SCI 2001, Orlando (Florida), July 22-25, 2001.

  43. A. Nannarelli, M. Re, G. C. Cardarilli, R. Lojacono, High Speed RNS A/D Front End, Imeko 2001, 6th Euro Workshop on ADC Modeling and Testing, pp.19-22, Lisboa (Portugal), 13-14 September, 2001.

  44. P. Da Ponte, M.Re, R. Lojacono, G.C. Cardarilli, UMTS Signal Analyser Based on a TFR and a FPGA Architecture, Fourth International Symposioum on Wireless Personal Multimedia Communications (WPMC'01), Alborg, Denmark.

  45. G. C. Cardarilli, M. Re, A. Del Re, V. Piloni Digital Demultiplexing Architecture for Satellite Applications, DSP 2001 Seventh International Workshop on Digital Signal Processing Techniques for Space Communications.

  46. G. Boscagli, L. Simone, C.M. Comparini, D. Gelfusa, M.Re, A. Del Re, G. Cardarilli, Programmable GMSK Modulator, 2nd ESA Workshop on Tracking Telemetry And Command Systems for Space Applications TTC 2001, 2nd ESA Workshop on Tracking Telemetry and Command Systems for Space Applications, 29-31 October 2001 ESTEC Noordwijk The Netherlands

  47. G. Boscagli, L. Simone, C.M. Comparini, D. Gelfusa, M.Re,A. Del Re, G. Cardarilli, Direct Digital Frequency Synthesis Techniques in the View of Implementation on FPGA, 2nd ESA Workshop on Tracking Telemetry And Command Systems for Space Applications TTC 2001, 2nd ESA Workshop on Tracking Telemetry and Command Systems for Space Applications, 29-31 October 2001 ESTEC Noordwijk The Netherlands

  48. M. Re, G. C. Cardarilli, A. Nannarelli, Implementation of Digital Filters in Carry Save Residue Number System Thirty-Fifth Asilomar Conference on Signals Systems and Computers,Vol. 2, pp. 1309-1313, Pacific Groove (California), October 29-November 4-7, 2001.

  49. Andrea Del Re, Alberto Nannarelli and Marco Re Fast Prototyping Techniques Applied to the Hardware Simulation of Telecommunication Systems Thirty-Fifth Asilomar Conference on Signals Systems and Computers, Pacific Groove (California), Vol. 2, pp. 1314-1317, October 29-November 4-7, 2001.

  50. G.C. Cardarilli, A. Nannarelli, M. Re, A. Del Re, Residue Number System Reconfigurable Data Path, IEEE ISCAS 2002, International Symposium on Circuits and Systems, Vol. 2 ,PP. 756-759 , 26-29 May 2002, Scottsdale, Arizona.

  51. G.C. Cardarilli, A. Nannarelli,M. Re, A. Del Re, Power Characterization of Digital Filters Implemented on FPGA , IEEE ISCAS 2002, International Symposium on Circuits and Systems, Vol. 5 ,PP.801-804, 26-29 May 2002, Scottsdale, Arizona.

  52. M. Ottavi G. C. Cardarilli, S. Pontarelli, M. Re, A. Salsano, A Self-Checking Cell Logic Block for Fault Tolerant FPGAs , IEEE ISCAS 2002, International Symposium on Circuits and Systems, Vol. 4 ,PP. 477-480, 26-29 May 2002, Scottsdale, Arizona.

  53. G.C. Cardarilli, A. Del Re, R. Lojacono, A. Nannarelli, M. Re, Performance comparison between traditional and RNS-based ADC, 4 th International Conference on Advanced A/D and D/A Conversion Techniques and their applications & 7th European Workshop on ADC Modeling and Testing, IMEKO 2002, EWADC WORKSHOP, June 26-28, Prague.

  54. P. Altamura , G.C. Cardarilli, A. Del Re, M. Re, OFDM Modem for ATM Based Point-Multipoint Systems, Proceedings of the 1 st IEEE International Conference on Circuits and Systems for Communications, pp. 138-141, 26-28 June, 2002, St. Petersburg, Russia.

  55. G. Cardarilli , A. Del Re, D. Giancristofaro, M. Re, L. Simone, Digital Modulator Architectures for Satellite and Space Applications, Proceedings of the 1 st IEEE International Conference on Circuits and Systems for Communications, pp. 166-169, 26-28 June, 2002, St. Petersburg, Russia.

  56. A. Bartolazzi, G. Cardarilli, A. Del Re, D. Giancristofaro, M. Re, Implementation of DVB-RCS Turbo Decoder for Satellite ON-BOARD Processing, Proceedings of the 1 st IEEE International Conference on Circuits and Systems for Communications, pp. 142-145, 26-28 June, 2002, St. Petersburg, Russia.

    Pubblicazioni su Rivista Nazionale

  57. M. Re, Progettare Circuiti Stampati con un PC, Elettronica Oggi, pp. 105-113, No. 57, 31 Marzo 1988.

  58. M. Re, CAE per Analisi circuitale, Elettronica Oggi, pp. 161-167, No. 103, 30 Giugno 1990.

    Pubblicazioni su Rivista Internazionale

  59. G. C. Cardarilli, M. Re, R. Lojacono, RNS-to-Binary Conversion for Efficient VLSI Implementation, IEEE Trans. Circuits Systems-I, Vol. 45, pp. 667-669, No 6, June, 1998.

  60. G.C. Cardarilli, M. Re, R. Lojacono, VLSI Implementation of a Real Time Fuzzy Processor, Journal of Intelligent & Fuzzy Systems, No.3, pp.389-401.Vol. 6, 1998, WILEY.

  61. G. C. Cardarilli, M. Re, G.Ferri, CMOS and Bipolar Novel Low-Power Adaptive Biasing Topologies, Microelectronics Journal, Vol. 30, No. 3, pp.223-227, Elsevier, 1999.

  62. G. C. Cardarilli, M. Re, G.Ferri, Low-power CMOS OTA input stages and voltage buffers based on adaptive biasing topology , Microelectronics Journal, Vol. 31, No. 3, pp.153-159, Elsevier, 2000.

  63. G.C.Cardarilli, G.Ferri, M.Re, Rail-to-Rail Adaptive Biased Low Power OP-AMP, Microelectronics Journal, pp. 265-272, Vol 32/3.

  64. G. C. Cardarilli, M. Re, R. Lojacono, G.Ferri, A Systolic Architecture for High Performance Scaled Residue to Binary Conversion, IEEE Trans. Circuits Systems-I, pp. 1523-1526, Vol. 47 No. 10, October, 2000.

    Capitoli di libri

  65. G. C Cardarilli, Marco Re, Roberto Lojacono , High Performance Fuzzy Processors, in "Hardware Implementataion of Intelligent Systems" by Horia-Nicolai Teodorescu, lakhmi C. Jain, Abram Kandel (Editors) Chapt. 4, pp.121-146, Physica Verlag, 2001.

  66. G.C. Cardarilli, M. Re, R. Lojacono, M. Salerno, Efficient VLSI Architecture for Residue to Binary Converter, published in the book Älgorithms and Parallel VLSI Architectures,"(raccolta selezionata di articoli) pp. 109-115, Elsevier, 1995.

    Lista pubblicazioni accettate: riviste

  67. Marco Re, Andrea Del Re, GianCarlo Cardarilli, Efficient Implementation of a Demultiplexer Based on a Multirate Filter Bank for the Skyplex Satellites DVB System, VLSI Design Journal. scheduled for vol 15/ no 1/ 2003.

  68. R. Lojacono, M. Re, M. Caciotta,F. Leccese, D. Petri, A. Moschitta, C. Gennarelli, G. Riccio, P. Daponte, S. Rapuano, D. Grimaldi, S. Graziani, S. Sangiovanni, Perspectives of QoS Management Based on QoAS for 3G communication systems, Wireless Personal Communications, Kluwer Academic Publisher.

    Lista pubblicazioni accettate: Congressi

  69. R. Lojacono, M. Re, a. Del Re, S. Sangiovanni, QoAS evaluation algorithms for improving QoS of 3G communications systems, WPMC' 02 The 5th International Symposium on Wireless Personal Multimedia Communications October 27-30, 2002, Sheraton Waikiki, Honolulu, Hawaii.

    Lista Congressi in attesa di accettazione

  70. G. Cardarilli, A. Del Re, R. Lojacono, M. Re , RNS Implementation of High Performance Demultiplexer for Satellite Application Journal of VLSI Signal Processing, 2003 IEEE Aerospace Conference.

  71. M. Ottavi, G. C. Cardarilli, S. Pontarelli, M. Re, A. Salsano, A Fault Tolerant Hardware Based File System Manager for Solid State Mass Memory, IEEE ISCAS 2003, International Symposium on Circuits and Systems,

  72. G. C. Cardarilli, A. Del Re, M. Re, IP based Reconfigurable Platform for Satellite Communications, IEEE ISCAS 2003, International Symposium on Circuits and Systems,

  73. G. C. Cardarilli, A. Nannarelli, M. Re, Power Delay Tradeoffs in Residue Number System, IEEE ISCAS 2003, International Symposium on Circuits and Systems,

    Lista Riviste in attesa di accettazione

  74. Marco Re and Giancarlo Cardarilli, A Generalized Algorithm for 3 Moduli CRT Based Conversion Journal of VLSI Signal Processing, Kluwer.



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